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This documentation is for a legacy ScanImage version. The current documentation is ScanImage 2019.
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I2C is a simple two wire serial bus. To synchronize a behavioral experiment with imaging, ScanImage can act as a I2C bus slave. When an event occurs, the controller of the behavioral experiment can send data bytes to ScanImage. ScanImage will timestamp the incoming packet and log the data bytes to the Tiff header of the appropriate image frame. To learn more about the I2C protocol, review the I2C Wikipedia article.


This feature is Resonant Scanning (ResScan) only.






The I2C bus is directly monitored by the ScanImage FPGA. A NI SCB-19 breakout box ix required to connect the bus to the FPGA. The I2C bus requires both the Serial Data Line (SDA) and Serial Clock Line (SCL) to be pulled to VDD. For this purpose, +5V pin of the SCB-19 serve as VDD. To calculate a resistance value for the pull-up resistors, please review this resource.


SCB-19 PinBus line
+5VVDD (optional)

I2C devices use open-drain terminals for SDA and SCL. This means they can only pull the bus lines to low, but rely on the pull up resistors to reset the lines to VDD. If a device is used to emulate an I2C master that can actively drive the bus (i.e. a NI-DAQ board), no pull-up resistors are required.

I2C wiring

Sample wiring diagram for ScanImage as I2C slave. SDA and SCL are pulled to VDD via pull up resistors Rp.


To configure ScanImage as an I2C slave, add the following lines to the 'ResScan' section of the Machine Data File:


I2C packet format


I2C sample packet

Sample of an I2C data package sent by the I2C master to an I2C slave. The transmission starts when the master pulls SDA to low while SCL is high. The master generates the clock and the ScanImage FPGA samples SDA on the rising edge of SCL. SDA needs to remain at a stable logic level for the entire duration of SCL high. The first byte sent by the master is the address of the slave. The following bytes are data bytes. The slave confirms receiving the byte by pulling SDA to low after the last bit in the byte. At the end of the transmission or if the transmission fails, the master releases SDA while SCL is high.


On the I2C bus a byte is transmitted with the most significant bit first.

Data format

ScanImage saves received packets in the Tiff header of the appropriate image frame. When a start of packet signal is registered on the I2C bus, the FPGA generates a high precision time stamp which is saved with the data to the frame header. Depending on the Machine Data File setting 'I2CStoreAsChar' ScanImage stores the packet either as 'binary' byte array (each byte is a value of 0-255) or as string. If saved as a string, a received byte of value 0 is interpreted as the end of string.

Tiff frame header for I2CStoreAsChar = false
Tiff frame header for I2CStoreAsChar = true

Emulate I2C master using a NI-DAQ board

A Matlab example using an NI-DAQ board as an I2C master can be downloaded here.


At the end of each transmitted byte, the I2C master and slave switch roles. To acknowledge the successful transmission of one byte, the I2C slaves pulls SDA to low during one SCL clock cycle.

If a NI-DAQ board is used to emulate an I2C master, this output can be deactivated so that ScanImage never actively drives SDA. This can reduce the risk of short circuit. To deactivate the ACK output, set the following parameter in the Machine Data File:

I2CDisableAckOutput = true;

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